1. Field
The following description relates to a semiconductor device in a level shifter with an electrostatic discharge protection circuit. The following description also relates to a semiconductor chip to protect a thin gate oxide of such a semiconductor device from an Electrostatic Discharge (ESD) stress.
2. Description of Related Art
A level shifter refers to a circuit configured to change a voltage level of a semiconductor chip interior, such as a Display Drive IC (DDI). For example, the level shifter converts a low voltage signal to a medium or high voltage signal. Thus, the level shifter is positioned between multiple power supply lines with high and low voltage inputs, and changes voltage appropriately as needed.
A semiconductor device in a level shifter is placed in a level shifter block that may not provide enough driving current because a gate input voltage is at too low a voltage. This situation occurs because there is a limit in increasing a driving current since a thick gate insulating layer is used in such a situation.
Accordingly, a semiconductor device in a level shifter with a relatively thin gate insulating layer may be used, but such semiconductor device in a level shifter is vulnerable to an ESD stress. The vulnerability occurs because, when ESD stress or Electrical Over-Stress, hereinafter referred to as “EOS”, is applied to the semiconductor device in a level shifter, a thin gate insulating layer is easily destroyed. Hence, an ESD protection circuit and device is necessary to prevent or block the ESD stress of a semiconductor device from occurring in a level shifter and damaging the thin gate insulating layer.